HD74HC375 Datasheet | Hitachi Semiconductor

Description This latch is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable goes high. Features - - - - - High Speed Operation: tpd (Data to Q, Q) = 10 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs D L H X G H H L Outputs Q L H no change Q H L no change Pin Arrangement 1D 1 1Q 2 1Q 3 Enable 1 to 2 4 2Q 5 2Q 6 2D 7 GND 8 (Top view) Q C Q D C Q D Q Q D Q C D Q C Q 16 VCC 15 4D 14 4Q 13 4Q 12 Enable 3 to 4 11 3Q 10 3Q 9 3D DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5 6.0 - 1.8 - 1.9 4.4 5.9 4.13 5.63 - - - Output voltage 2.0 4.5 6.0 4.5...