HD74HC393 Datasheet | Hitachi Semiconductor

Description The HD74HC393 contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter. The HD74HC393 is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. when clear is set high all four bits of each counter are set to a low level. This enables count trucation and allows the implementation of divide-by-N counter configurations. Features - - - - - High Speed Operation: tpd (A to QA) = 16 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Clock X H L Clear H L L L L Outputs L No change No change No change Advance to next state Pin Arrangement 1A 1Clear 1QA 1QB 1QC 1QD GND 1 2 3 4 5 6 7 CLR QA QB A A QC QD QC QD CLR QA QB 14 13 12 11 10 9 8 VCC 2A 2Clear 2QA 2QB 2QC 2QD Outputs (Top view) Outputs Block Diagram (1/2) Clock C D Clear DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15...