HD74HC4040 Datasheet | Hitachi Semiconductor

Description The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Features - - - - - High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table C Reset L L X X: Irrelevant H Outputs State No change Advance to next stage All outputs are low Pin Arrangement Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND 1 2 3 4 5 6 7 8 (Top view) Q6 Q5 Q7 Q4 Q3 Q2 Q12 Q11 Q10 Q8 Q9 Reset Clock 16 VCC 15 Q11 14 Q10 13 Q8 12 Q9 11 R 10 C 9 Q1 Q1 Block Diagram Q1 Clock C Q C Q R Reset C Q C Q R Q2 C Q C Q R Q3 C Q C Q R Q10 C Q C Q R Q11 C Q C R Q12 Timing Diagram Clock Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 1 2 4 8 16 32 64 128 256 512 1,024 2,048 4,096 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5...