HD74HC4520 Datasheet | Hitachi Semiconductor

Description The HD74HC4518 dual BCD counter and the HD74HC4520 dual binary counter consist of two identical, independent, internally synchronous 4-stage counters. The counter stages are type D flip-flops, with interchangeable Clock and Enable lines for incrementing on either the positive-going or negative-going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the HD74HC4518 will count out of all undefined states within two clock periods. These plementary MOS up counters find primary use in multi-stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. Features - - - - - High Speed Operation High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Clock Enable H L X X L H X X Reset L L L L L L H Operation Increment counter Increment counter No change No change No change No change Q0 to Q 3 = L HD74HC4518/HD74HC4520 Pin Arrangement Clock A Enable A Q0 A Q1 A Q2 A Q3 A Reset A GND 1 2 3 4 5 6 7 8 (Top view) C Q0 Q1 Q2 Q3 R R Q3 Q2 Q1 Q0 C 16 VCC 15 Reset B 14 Q3 B 13 Q2 B 12 Q1 B 11 Q0 B 10 Enable B 9 Clock B HD74HC4518/HD74HC4520 Timing Diagram 1 Clock Enable Reset 1 Q0 Q1 HD74HC4518 Q2 Q3 Q0 Q1 HD74HC4520 Q2 Q3 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 5 6 9 10 11 12 13 14 15 0 3 4 HD74HC4518/HD74HC4520 Logic Diagram HD74HC4518 Q0 Q1 Q2...