HD74HC597 Datasheet | Hitachi Semiconductor

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features - - - - - High Speed Operation: tpd (SCK to QH’) = 14 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table RCK SCK X X X X X X X X X SLoad X L L L H H SCLR X H H L L H Function Data loaded to input latches Data loaded from inputs to shift register Data transferred from input latches to shift register Invalid logic, state of shift register indeterminate when signals removed Shift register cleared Shift register clocked Qn = Qn - 1, QA = SER Pin Arrangement B 1 C 2 D 3 E 4 F 5 G 6 H 7 GND 8 (Top view) 16 VCC 15 A 14 SER 13 S Load 12 RCK 11 SCK 10 SCLR 9 Q'H Logic Diagram SCLR SLoad RCK SER SCK DQ C SC D Q R DQ C SC D Q R C D E F G H DQ C SC D Q R Q'H DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - -...