HD74HC652 Datasheet | Hitachi Semiconductor

Description This device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Enable GAB and GBA are provided to cotrol the transceiver functions. Select AB and Select BA control pins are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the HD74HC651 and HD74HC652. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to high transition at the appropriate clock pins (Clock AB or Clock BA) regardless of the select or enable control pins. When Select AB and Select BA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Enable GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. Features - - - - - High Speed Operation: tpd (Bus to Bus) = 16 ns typ (CL = 50 p F) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC651/HD74HC652 Function Table Real-Time Transfer Real-Time Transfer Bus B to Bus A Bus A to Bus B Storage Clock AB Select AB Enable GAB Clock BA Select BA Enable GBA X X L X L L X L H X X H X H X L Transfer Stored Data to A and/or B L or H H H L or H H L Bus A Bus A Bus B Real-time transfer Bus B to Bus A Real-time transfer Bus A to Bus B Bus B HD74HC651/HD74HC652 Bus A Bus A Bus B Storage Transfer stored data to A and/or B Pin Arrangement Clock AB Select AB Enable GAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5...