HD74HC668 Datasheet | Hitachi Semiconductor

Description This synchronous presettable decade counter features an internal carry look-ahead for cascading in highspeed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in acplishing this function are two count enable inputs and a carry output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input. when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the Q A output when counting up and approximately equal to the low portion of the QA output when counting down. This low level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transissionline effects, thereby simplifying system design. This counter features a fully independent...