HD74HC677 Datasheet | Hitachi Semiconductor

Description The HD74HC677 address parator simplifies addressing of memory boards and/or other peripheral devices. The four P inputs are normally hard wired with a preprogrammed address. An internal decoder determines what input infomation applied to the 16 A inputs must be low or high to cause a low state at the output (Y). For example, a positive-logic bit bination of 0111 (decimal 7) at the P input determines that inputs A1 through A7 must be low and that inputs A8 through A16 must be high to cause the output to go low. Equality of the address applied at the A inputs to the preprogrammed address is indicated by the output being low. The HD74HC677 features an enable input (G). When G is low, the device is enabled. When G is high, the device is disabled and the output is high regardless of the A and P inputs. Features - - - - - High Speed Operation: tpd (A to Y) = 17 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs G L L L L L L L L L L L L L L L L L H P3 P2 P1 P0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Output Y L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H H L L L L L L L L L L L L L L L H H L L L L L L L L L L L L L L H H H L L L L L L L L L L L L L H H H H L L L L L L L L L L L L H H H H H L L L L L L L L L L L H H H H H H L L L L L L L L L L H H H H H H H L L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H H L L L L L L L H H H H H H H H H H L L L L L L H H H H H H H H H H H L L L L L H H H H H H H H H H H H L L L L H H H H H H H H H H H H H L L L H H H H H H H H H H H H H H L L H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L H H All other binations Any bination Pin Arrangement A1 A2 A3 A4 A5 A6 A7 A8 A9 1 2...