HD74HC680 Datasheet | Hitachi Semiconductor

Description The HD74HC680 address parator simplifies addressing of memory boards and/or other peripheral devices. The four P inputs are normally hard wired with a preprogrammed address. An internal decoder determines what input information applied to the 12 A inputs must be low or high to cause a low state at the output (Y). For example, a positive-logic bit bination of 0111 (decimal 7) at the P input determines that inputs A1 through A7 must be low and that inputs A8 through A12 must be high to cause the output to go low. Equality of the address applied at the A inputs to the preprogrammed address is indicated by the output being low. The HD74HC680 features a transparent latch and a latch enable input (C). When C is high, the device is in the transparent mode. When C is low, the previous logical state of Y is latched. Features - - - - - High Speed Operation High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs C H H H H H H H H H H H H H H H H H L P3 L L L L L L L L H H H H H H H H P2 L L L L H H H H L L L L H H H H P1 L L H H L L H H L L H H L L H H P0 L H L H L H L H L H L H L H L H A1 H L L L L L L L L L L L L X X L A2 H H L L L L L L L L L L L X X L A3 H H H L L L L L L L L L L X X L A4 H H H H L L L L L L L L L X X L A5 H H H H H L L L L L L L L X X L A6 H H H H H H L L L L L L L X X L A7 H H H H H H H L L L L L L X X L A8 H H H H H H H H L L L L L X X L A9 H H H H H H H H H L L L L X X L A10 A11 A12 H H H H H H H H H H L L L X X L H H H H H H H H H H H L L X X L H H H H H H H H H H H H L X X L Output Y L L L L L L L L L L L L L H H L H Latched All other binations Any bination Pin Arrangement A1 A2 A3 A4 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 20 VCC 19 C 18 Y 17 P3 16 P2 15 P1 14 P0 13 A12 12 A11 11 A10 (Top view) GND 10 Logic Diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 IN A11...