HD74HC688 Datasheet | Hitachi Semiconductor

Description The HD74HC688 pares bit for bit two 8-bit words and indicates whether or not they are equal. The P=Q output indicates equality when it is low. A single active low enable is provided to facilitate cascading of several packages and enable parison of words greater than 8-bits. This device is useful in memory block decoding applications, where memory block enable signals must be generated from puter address information. Features - - - - - High Speed Operation: tpd (P or Q to Output) = 17 ns typ (C L = 50 p F High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Input Data P, Q P=Q P>Q P<Q X Enable G L L L H P=Q L H H H Pin Arrangement G P0 Q0 P1 Q1 P2 Q2 P3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 P=Q 18 Q7 17 P7 16 Q6 15 P6 14 Q5 13 P5 12 Q4 11 Q4 GND 10 (Top view) Block Diagram P0 Q0 P1 Q1 P2 Q2 P3 Q3 P4 P=Q Q4 P5 Q5 P6 Q6 P7 Q7 G DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5...