HD74HC74 Datasheet | Hitachi Semiconductor

Description The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and acplished by a low level on the input. Features - - - - - High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Clear L H H H H H H H L H Clock X J X L L H H X X X K X L H L H X X X Outputs Q L No change L H Toggle No change No change No change H L Q H HD74HC73 Pin Arrangement 1CK 1 CLR 1CLR 2 1K 3 VCC 4 2CK 5 2CLR 6 2J 7 K CK J CLR Q Q J CK K Q Q 14 1J 13 1Q 12 1Q 11 GND 10 2K 9 2Q 8 2Q (Top view) Block Diagram Q CK CK Q K CK CK CK CK CLR J CK CK CK CK HD74HC73 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 20 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5...