HD74LV166A Datasheet | Hitachi Semiconductor

Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by bining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook puters), and the low-power consumption extends the battery life. Features - - - - - - VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 m A (@VCC = 3.0 V to 3.6 V), ±12 m A (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLR L H H H H H SH/LD X X L H H X CLK INH X L L L L H CLK X L ↑ ↑ ↑ ↑ SER X X X H L X A ... H X X a ... h X X X Internal outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0 Note: H: High level L: Low level ↑: Low to high transition X: Immaterial a ... h: Parallel data QA0 ... Q H0: Outputs remain unchanged. QAn ... Q Gn : Data shifted from the previous stage on a positive edge at the clock input. Pin Arrangement SER 1 A 2 B 3 C 4 D 5 CLK INH 6 CLK 7 GND 8 16 VCC 15 SH/LD 14 H 13 QH 12 G 11 F 10 E 9 CLR (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range- 1 1, 2 Symbol VCC VI VO Ratings - 0.5 to 7.0 - 0.5 to 7.0 - 0.5 to VCC + 0.5 - 0.5 to 7.0 Unit V V V Conditions Output voltage range- Output: H or L VCC: OFF Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum...