HD74LV393A Datasheet | Hitachi Semiconductor

Description The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter. The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count trucation and allows the implementation of divide-by-N counter configurations. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook puters), and the low-power consumption extends the battery life. Features - - - - - - VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 m A (@VCC = 3.0 V to 3.6 V), ±12 m A (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLK X H L ↑ ↓ Note: H: L: X: ↑: ↓: High level Low level Immaterial Low to high transition High to low transition CLR H L L L L Output L No change No change No change Count up Pin Arrangement 1CLK 1 1CLR 2 1QA 3 1QB 4 1QC 5 1QD 6 GND 7 14 VCC 13 2CLK 12 2CLR 11 2QA 10 2QB 9 2QC 8 2QD (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range- 1 1, 2 Symbol VCC VI VO Ratings - 0.5 to 7.0 - 0.5 to 7.0 - 0.5 to VCC + 0.5 - 0.5 to 7.0 Unit V V V Conditions Output voltage range- Output: H or L VCC: OFF Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)- 3 I IK I OK IO I CC or IGND PT - 20 ±50 ±25 ±70 785 500 m A m A m A m A m W VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP Storage temperature Tstg - 65 to 150 °C Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be...