HD74LV573A Datasheet | Hitachi Semiconductor

Description The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook puters), and the low-power consumption extends the battery life. Features - - - - - - VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±8 m A (@VCC = 3.0 V to 3.6 V), ±16 m A (@VCC = 4.5 V to 5.5 V) Function Table Inputs OE L L L H Note: H: L: X: Z: Q0 : LE H H L X D H L X X Output Q H L Q0 Z High level Low level Immaterial High impedance Output level before the indicated steady state input conditions were established Pin Arrangement OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range- 1 1, 2 Symbol VCC VI VO Ratings - 0.5 to 7.0 - 0.5 to 7.0 - 0.5 to VCC + 0.5 - 0.5 to 7.0 Unit V V V Conditions Output voltage range- Output: H or L VCC: Z or VCC: OFF Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)- 3 I IK I OK IO I CC or IGND PT - 20 ±50 ±35 ±70 835 757 m A m A m A m A m W VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP Storage temperature Tstg - 65 to 150 °C Notes: The absolute...