HM5212325FBPC-B60 Datasheet | Hitachi Semiconductor

Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. Features - - - - - - - - - Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch  Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence  Sequential (BL = 4/8/full page)  Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms - - - HM5212325FBPC-B60 - 2 variations of refresh  Auto refresh  Self refresh - Full page burst length capability  Sequential burst  Burst stop capability Ordering Information Type No. HM5212325FBPC-B60- Frequency 100 MHz CAS latency 3 Package 10 mm × 13 mm 90 bump FBGA (BP-90) Note: 66 MHz operation at CAS latency = 2. Pin Arrangement 90-bump FBGA 1 A B C D E F G H J K L M N P Q DQ15 DQ0 DQ14 DQ13 DQ2 DQ1 DQ12 DQ11 DQ4 DQ3 DQ10 DQ9 DQ6...