HMC848LC5 Description
The HMC848LC5 is a 1:4 demultiplexer designed for data deserialization up to 45 Gbps. The device uses both rising and falling edges of the half-rate clock to sample the input data in sequence, D0-D3 and latches the data onto the differential outputs. A quarter-rate clock output generated on-chip can be used to clock the data into other devices.