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HI-8685 - (HI-8685 / HI-8686) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 16-BIT PARALLEL DATA

General Description

The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology.

Both products incorporate the digital logic and analog line receiver circuitry in a single device.

Key Features

  • ! Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data HI-8685 28-Pin Plastic SOIC - WB Package ! High speed parallel 16-bit data bus ! Error detection - word length and parity ! Reset input for power-on initialization ! On-chip line receiver ! Input hysteresis of at least 2 volts ! Test lnputs bypass analog inputs ! Simplified lightning protection with the ability to add 10 Kohm external series resistors SOIC, TQFP and PLCC N/C - 1 D12 - 2 D11 - 3 D10 - 4 D9 - 5 D.

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Datasheet Details

Part number HI-8685
Manufacturer Holt Integrated Circuits
File Size 239.36 KB
Description (HI-8685 / HI-8686) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 16-BIT PARALLEL DATA
Datasheet download datasheet HI-8685 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HI-8685, HI-8686 February 2001 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data PIN CONFIGURATIONS (Top View) DATARDY D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Vcc GAPCLK TESTA TESTB RESET RINB (-10) RINA (-10) ERROR PARITY ENB READ D0 D1 D2 D3 DESCRIPTION The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology. Both products incorporate the digital logic and analog line receiver circuitry in a single device. The receivers on the HI-8685 and the HI-8686 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.