HT6560A Datasheet | Holtek Microelectronics

- 6560A VL_BUS IDE CONTROLLER A. General Description - JAN.04.1994 PAGE: 1 HT- 6560A is a VL_Bus IDE controller which provides a control logic and data path between 486, 386 VL_Bus and IDE drives. The HT- 6560A is fully patible with the ANSI ATA revision 3.0 specification for IDE hard disk operation and VESA VL_Bus revision 1.0 specification for local bus PC drives. The HT- 6560A is a high performance and fully design for IDE application. At the host CPU interface, HT- 6560A provides a posted write and pre-fetched read fully 32 bits data path. It can operate up to 50 MHz and zero wait-state cycle. Double word read and write operations are provided. It also allows concurrent IDE and CPU memory operations to maximize system performance. Flexible IDE drive interface timing selection. Power on reset latch the adequate IDE active and recovery time into config register. HT- 6560A also allows you detect IDE performance and change the config register by software program or BIOS. B. Features - - - - - - - - - - - VESA VL_Bus rev 1.0 patible. Connects directly to VL_Bus and IDE interface no extra TTL needed. Supports 16 bits and 32 bits data transfer. Zero wait_state 50MHz operation. Support read pre-fetch, posted write and I/O channel ready function. Support various type of ANSI ATA patible IDE drives. Program mable mand active and recovery time. Support primary and secondary I/O port selection. 100-pin PQFP package. BIOS and software driver supported. - 6560A VL_BUS IDE CONTROLLER C. Block Diagram - JAN.04.1994 PAGE: 2 D. Pin Assignment - HT - 6560A VL_BUS IDE CONTROLLER E. Pin Description - Pin No. 1 Pin Name HCI I/O I Description JAN.04.1994 PAGE: 3 mand recovery time counter bit 1. This signal is negated to extend the host transfer cycle of any host mand or data register access when the drive is not ready to respond to a data transfer request. When IORDY is not negated, IOCHRDY is in a high impedance state. +5V POWER. GROUND. Drive I/O read...