Description
Host Interface Signal
Pin No
14~16 17 11 9 24~28, 20~22 10 19 18 8 13 7
Pin Name
A0~A2 CS DACK DRQ D0~D7 EOP IOR IOW IRQ READY RESET
I/O
I I I O I/O I I I O O I Address Lines Chip Select, active low
Description
DMA Acknowledge, active low DMA Request Data Lines End of Process, active low I/O Re
Features
- Support the ANSI X3.131-1986 standard Asynchronous transfer rate to 5 Mbyte/sec Support initiator and target mode 0.8um CMOS process.
- On chip 48mA single-ended drivers and receivers Non internal clock needed 44pins PLCC package
Block Diagram
1
14th July ’97
HT6576A
Pin Diagram
Pin.
HT6576A Datasheet
