GENERAL DESCRIPTION
The device operates at a frequency of up to 60 MHz with a Flash accelerator to obtain maximum efficiency. The device provides 32 KB of embedded Flash memory for code/data storage and 8 KB of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as Hardware Divider DIV, PDMA, ADC, OPA, PGA, CMP, I2C, UART, SPI, MCTM, GPTM, SCTM, BFTM, CRC-16/32, 96-bit Unique ID, LSTM, WDT, SW-DP (Serial Wire Debug Port), etc., are also implemented in the device. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The device also includes a 32 V 3-channel half-bridge driver with isolated motor current sensing function and can drive a three-phase BLDC motor. The driver has several internal protection functions and integrates an accurate 5 V output LDO with very low quiescent current. The above features...