HR2000 Datasheet | Honeywell

FEATURES - Fabricated on Honeywell’s Radiation Hardened 0.65 µm Leff RICMOS™ IV Bulk Process - Array Sizes from 10K to 336K Available Gates (Raw) - TTL or CMOS patible I/O - Full plement of Screening Flows .. FAMILY - Total Dose Hardness ≥1x106 rad(Si O2) - Dose Rate Upset Hardness ≥1x109 rad(Si)/sec - Dose Rate Survivability ≥1x1012 rad (Si)/sec - Soft Error Rate ≤1x10-10 Errors/Bit/Day - Neutron Fluence Hardness to 1x1014/cm2 - No Latchup - Configurable Multi-Port Gate Array SRAM - Modular Custom Drop-In SRAM Capability - Supports 5V Operation - Supports System Speeds Beyond 75 MHz GENERAL DESCRIPTION The HR2000 gate arrays are performance oriented seaof-transistor arrays, fabricated on Honeywell’s 0.65 µm RICMOS™ IV bulk CMOS process. The high density and performance characteristics of the RICMOS (Radiation Insensitive CMOS) process make possible device operation beyond 75 MHz over the full military temperature range, even after exposure to ionizing radiation exceeding 1x106 rad(Si O2). Flip-Flops have been designed for a Soft Error Rate (SER) of less than 1x10-10 errors/bit/day in the Adams 90% worst case environment. Each HR2000 design is founded on our proven RICMOS ASIC library of SSI and MSI logic elements, configurable RAM cells and selectable I/O pads. The gate arrays feature a global clock network capable of handling multiple clock signals with low clock skew between registers. This family is fully patible with Honeywell’s high reliability screening procedures and consistent with QML Class Q and V requirements. Designers can choose from a wide variety of I/O types. Output buffer options include 5 drive strengths, CMOS/ TTL levels, IEEE 1149.1 boundary scan, pull-up/pulldown resistors, and three-state capability. Input buffers can be selected with CMOS/TTL/Schmitt trigger levels, IEEE 1149.1 boundary scan and pull-up/pull-down resistors. Bi-directional buffers are also available. The HR2000 family provides options for configurable multi-port...