GM71V65163C Datasheet | SK Hynix

Description The GM71V(S)65163C/CL is the new generation dynamic RAM organized 4,196,304 words by 16 bits. The GM71V(S)65163C/CL utilizes advanced CMOS Silicon Gate Process Technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. System oriented features include single power supply of 3.3V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The GM71V(S)65163C/CL offers Extended Data Out(EDO) Mode as a high speed access mode. Pin Configuration 50 SOJ / TSOP-II VCC IO0 IO1 IO2 IO3 VCC IO4 IO5 IO6 IO7 NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS IO15 IO14 IO13 IO12 VSS IO11 IO10 IO9 IO8 NC VSS /LCAS /UCAS /OE NC NC NC A11 A10 A9 A8 A7 A6 VSS Features - 4,196,304 Words x 16 Bit - Extended Data Out (EDO) Mode Capability - Fast Access Time & Cycle Time (Unit: ns) /WE /RAS NC NC NC NC A0 A1 t RAC GM71V(S)65163C/CL-5 GM71V(S)65163C/CL-6 50 60 t AA 25 30 t CAC 13 15 t RC 90 110 t HPC 20 25 A2 A3 A4 A5 VCC m o c . u 4 t e e h s a t a .d w w w Rev 0.1 / Apr’01 - Power dissipation - Active : 540m W/504m W(MAX) - Standby : 1.8 m W ( CMOS level : MAX ) 0.54m W ( L-Version : MAX) - EDO page mode capability - Access time : 50ns/60ns (max) - Refresh cycles - RAS only Refresh 4096 cycles/64 ms (GM71V65163C) 4096 cycles/128ms (GM71VS65163CL)(L_Version) - CBR & Hidden Refresh 4096 cycles/64 ms (GM71V65163C) 4096 cycles/128 ms (GM71VS65163CL)( L-Version ) - 4 variations of refresh -RAS-only refresh -CAS-before-RAS refresh -Hidden refresh -Self refresh (L-Version) - Single Power Supply of 3.3V+/-10 % with a built-in VBB generator - Battery Back Up Operation ( L-Version ) (Top View) .. GM71V65163C GM71VS65163CL Pin Description Pin A0-A11 A0-A11 RAS UCAS,LCAS OE Function Address Inputs Refresh Address Inputs Row Address Strobe Column Address Strobe Output Enable Pin WE I/O0...