H5TC2G43EFR-xxA
Description
The H5TC2G43EFR-xxA and H5TC2G83EFR-xxA are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V.
Key Features
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK
- JEDEC standard 78ball FBGA(x4/x8) transition
- Driver strength selected by EMRS
- DM masks write data-in at the both rising and falling
- Dynamic On Die Termination supported edges of the data strobe
- Asynchronous RESET pin supported
- All addresses and control inputs except data, data
