H5TC4G83MFR-xxA Overview
DDR3L SDRAM provides backward patibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data...
H5TC4G83MFR-xxA Key Features
- VDD=VDDQ=1.35V + 0.100 /
- 0.067V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK
- JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16) transition
- DM masks write data-in at the both rising and falling edges of the data strobe
