H5TQ2G63GFR-xxJ
Description
The H5TQ2G83GFR-xxC, H5TQ2G63GFR-xxC,H5TQ2G83GFR-xxI, H5TQ2G63GFR-xxI, H5TQ2G83GFRxxL,H5TQ2G63GFR-xxL,H5TQ2G83GFR-xxJ,H5TQ2G63GFR-xxJ are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
Key Features
- VDD=VDDQ=1.5V +/- 0.075V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- On chip DLL align DQ, DQS and DQS transition with CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable additive latency 0, CL-1, and CL-2 supported
- Programmable CAS Write latency (CWL) = 5, 6, 7, 8 9 and 10
- Programmable burst length 4/8 with both nibble sequential and interleave mode
- BL switch on the fly
