H5TQ2G83EFR-xxC SK Hynix Datasheet

H5TQ2G83EFR-xxC Key Features

• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
• Differential Data Strobe (DQS, DQS)
• 7.8 µs at 0oC ~ 85 oC
• 3.9 µs at 85oC ~ 95 oC
• On chip DLL align DQ, DQS and DQS transition with CK  transition
• JEDEC standard 78ball FBGA(x4/x8)
• DM masks write data-in at the both rising and falling  edges of the data strobe