H5TQ2G83EFR-xxC
Overview
The H5TQ2G43EFR-xxC, H5TQ2G83EFR-xxC are a 2Gb CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
- VDD=VDDQ=1.5V +/- 0.075V
- Fully differential clock inputs (CK, CK) operation
- 8banks
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- Differential Data Strobe (DQS, DQS) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK transition
- JEDEC standard 78ball FBGA(x4/x8)
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
