H5TQ4G63MFR-xxC
Overview
The H5TQ4G43MFR-xxC, H5TQC4G83MFR-xxC and H5TQ4G63MFR-xxC are a 4Gb CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
- VDD=VDDQ=1.5V + - 0.075V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK
- JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16) transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported
- Programmable additive latency
