H5TQ4G83BMR-xxC
Description
The H5TQ4G43BMR-xxC, H5TQ4G83BMR-xxC are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Key Features
- VDD=VDDQ=1.5V +/- 0.075V
- Fully differential clock inputs (CK, CK) operation
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- Differential Data Strobe (DQS, DQS) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK transition
- Auto Self Refresh supported
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable additive latency 0, CL-1, and CL-2 supported
- Programmable CAS Write latency (CWL) = 5, 6, 7, 8
