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HY57V651620B - 4 Banks x 1M x 16Bit Synchronous DRAM

General Description

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V641620HG is organized as 4banks of 1,048,576x16.

Key Features

  • Single 3.3±0.3V power supply Note).
  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch.
  • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst.
  • Programmable CAS Lat.

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Datasheet Details

Part number HY57V651620B
Manufacturer SK Hynix
File Size 81.92 KB
Description 4 Banks x 1M x 16Bit Synchronous DRAM
Datasheet download datasheet HY57V651620B Datasheet

Full PDF Text Transcription for HY57V651620B (Reference)

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HY57V651620B 4 Banks x 1M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory appli...

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64-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16. H Y 5 7 V 6 4 1 6 2 0 H G i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y nc h r o nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

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