HY5DU561622CT Description
and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
HY5DU561622CT Key Features
- VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK, /CK)
- data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per ea
- Note : D of speed indicates DDR400