HY5DU561622DT Datasheet | SK Hynix

description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1 .. HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T Revision History Revision No. History First Version Release Merged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Draft Date Remark Oct. 2004 Rev. 1.0 /Oct. 2004 .. HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T DESCRIPTION The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. - - - - - - - FEATURES VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +/- 0.1V for DDR400 All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported Programmable burst length 2/4/8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported t RAS lock out function supported 8192 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS - - - - - - - -...