HY5DU561622LTP Overview
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HY5DU561622LTP Key Features
- VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK,
- data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per ea
- X means speed grade
- CL1.5 @ DDR200 supported
- CL3 supported
