HY5DU561622LTP Datasheet PDF ((HY5DU56x22DTP) 256M DDR SDRAM) | Download Hynix Semiconductor HY5DU561622LTP

HY5DU561622LTP - (HY5DU56x22DTP) 256M DDR SDRAM

This page provides the datasheet information for the HY5DU561622LTP, a member of the HY5DU56422DTP (HY5DU56x22DTP) 256M DDR SDRAM family.

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

Datasheet Details

Part number	HY5DU561622LTP
Manufacturer	SK Hynix
File Size	450.52 KB
Description	(HY5DU56x22DTP) 256M DDR SDRAM
Datasheet	HY5DU561622LTP Datasheet
Additional preview pages of the HY5DU561622LTP datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP 256M DDR SDRAM HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 /May 2004 www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION PRELIMINARY The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.

Published: Nov 7, 2006 |