HY5DU561822ETP
description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /June. 2006 1
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HY5DU56822E(L)TP HY5DU561622E(L)TP
Revision History
Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark
Rev. 1.1 /June. 2006
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HY5DU56822E(L)TP HY5DU561622E(L)TP
DESCRIPTION
The HY5DU56822E(L)TP and HY5DU561622E(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both...
