HY5S5B2BLF-HE Datasheet | SK Hynix

description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 : 85m A --> 90m A 133MHz IDD1 : 70m A --> 75m A 105MHz IDD1 : 50m A --> 60m A 2. Remove CL2 operation (Page 13 to 14) 1. Release History Draft Date Nov. 2005 Remark Preliminary Mar. 2006 Preliminary Apr. 2006 Final Rev 1.0 / Apr. 2006 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series DESCRIPTION The Hynix HY5S5B2BLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the mands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is partible with the 2n rule of prefetch architectures, but it...