HYMP112P72CP8L-C4
description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / May. 2008 1
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1240pin DDR2 VLP Registered DIMMs FEATURES
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- - JEDEC standard 1.8V +/- 0.1V Power Supply VDDQ : 1.8V +/- 0.1V All inputs and outputs are patible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Average Auto Refresh Period 7.8us under TCASE 85 , 3.9us at 85 High Temperature Self-Refresh Entry enablble features
PASR(Partial Array Self- Refresh) 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA 133.35 x 18.29 mm form factor Lead-free Products are Ro HS pliant < TCASE...
