HYMP112U64CR8-Y5
FEATURES
- JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/
- 0.1V Power Supply All inputs and outputs are patible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK)
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- Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) 133.35 x 30.00 mm form factor Ro HS pliant
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- ORDERING INFORMATION
Part Name HYMP164U64CP6-C4/Y5/S6/S5 HYMP164U64CR6-C4/Y5/S6/S5 HYMP112U64CP8-C4/Y5/S6/S5 HYMP112U64CR8-C4/Y5/S6/S5 HYMP112U72CP8-C4/Y5/S6/S5 HYMP125U64CP8-C4/Y5/S6/S5 HYMP125U64CR8-C4/Y5/S6/S5 HYMP125U72CP8-C4/Y5/S6/S5 Density 512MB 512MB 1GB 1GB 1GB 2GB 2GB 2GB Org. 64Mx64 64Mx64 128Mx64 128Mx64 128Mx72 256Mx64 256Mx64...
