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HYMP125R72CP4-C4 - 240pin Registered DDR2 SDRAM DIMMs based on 1Gb

Download the HYMP125R72CP4-C4 datasheet PDF. This datasheet also covers the HYMP112P72CP8-C4 variant, as both devices belong to the same 240pin registered ddr2 sdram dimms based on 1gb family and are provided as variant models within a single manufacturer datasheet.

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination).
  • Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYMP112P72CP8-C4-HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYMP125R72CP4-C4
Manufacturer SK Hynix
File Size 256.88 KB
Description 240pin Registered DDR2 SDRAM DIMMs based on 1Gb
Datasheet download datasheet HYMP125R72CP4-C4 Datasheet

Full PDF Text Transcription for HYMP125R72CP4-C4 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYMP125R72CP4-C4. For precise diagrams, and layout, please refer to the original PDF.

240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Bal...

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Module (DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.

More Datasheets from SK Hynix

Part Number Description
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