HYMP125S64CP8 Datasheet | SK Hynix

FEATURES - JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply - All inputs and outputs are patible with SSTL_1.8 interface - - - Posted CAS Programmable CAS Latency 3 ,4 ,5, and 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) - Fully differential clock operations (CK & CK) - - - - - Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x8) , 84 ball(x16) FBGA - - 67.60 x 30.00 mm form factor Ro HS pliant ORDERING INFORMATION Part Name HYMP164S64CP6-C4/Y5/S5/S6 HYMP164S64CR6-C4/Y5/S5/S6 HYMP112S64CP6-C4/Y5/S5/S6 HYMP112S64CR6-C4/Y5/S5/S6 HYMP125S64CP8-C4/Y5/S5/S6 HYMP125S64CR8-C4/Y5/S5/S6 Density 512MB 512MB 1GB 1GB 2GB 2GB Organization 64Mx64 64Mx64 128Mx64 128Mx64 256Mx64 256Mx64 # of DRAMs 4 4 8 8 16 16 # of ranks 1 1 2 2 2 2 Materials Lead free Halogen free Lead free Halogen free Lead free Halogen free This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Dec. 2009 1 .. 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-t RCD-t RP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps t CK ADDRESS TABLE Density Organization Ranks 512MB 1GB 2GB 64M x 64 128M x 64 256M x 64 1 2 2 SDRAMs 64Mb x 16 64Mb x 16 128Mb x 8 # of DRAMs 4 8 16 # of row/bank/column Address 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms Rev. 1.0 / Dec. 2009 .. 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION Symbol Type Polarity Cross Point Pin Description The...