HYMP125U64CR8-Y5 Datasheet | SK Hynix

240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. Features - JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are patible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) - - - - - - - Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) 133.35 x 30.00 mm form factor Ro HS pliant - - - - - - - ORDERING INFORMATION Part Name HYMP164U64CP6-C4/Y5/S6/S5 HYMP164U64CR6-C4/Y5/S6/S5 HYMP112U64CP8-C4/Y5/S6/S5 HYMP112U64CR8-C4/Y5/S6/S5 HYMP112U72CP8-C4/Y5/S6/S5 HYMP125U64CP8-C4/Y5/S6/S5 HYMP125U64CR8-C4/Y5/S6/S5 HYMP125U72CP8-C4/Y5/S6/S5 Density 512MB 512MB 1GB 1GB 1GB 2GB 2GB 2GB Org. 64Mx64 64Mx64 128Mx64 128Mx64 128Mx72 256Mx64 256Mx64 256Mx72 # of DRAMs 4 4 8 8 9 16 16 18 # of ranks 1 1 1 1 1 2 2 2 Materials Lead-free Halogen-free Lead-free Halogen-free Lead-free Lead-free Halogen-free Lead-free ECC None None None None ECC None None ECC This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Jul. 2008 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6...