HMP31GP7AFR4C-S5 - 240pin Registered DDR2 SDRAM DIMMs based on 2Gb

This page provides the datasheet information for the HMP31GP7AFR4C-S5, a member of the HMP31GP7AFR4C-Y5 240pin Registered DDR2 SDRAM DIMMs based on 2Gb family.

Product Overview

Hynix

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Datasheet Details

Part number	HMP31GP7AFR4C-S5
Manufacturer	Hynix
File Size	190.03 KB
Description	240pin Registered DDR2 SDRAM DIMMs based on 2Gb
Datasheet	HMP31GP7AFR4C-S5 Datasheet
Additional preview pages of the HMP31GP7AFR4C-S5 datasheet.

HMP31GP7AFR4C-S5 Product details

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination).
Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode.

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Published: Oct 18, 2014 |