HYMP512S64CLP8-Y5 Datasheet | SK Hynix

FEATURES - JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are patible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK) - - - - - - - Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball(x8), 84ball(x16) FBGA 67.60 x 30.00 mm form factor Lead-free Products are Ro HS pliant - - - - - ORDERING INFORMATION Part Name HYMP532S64CP6-E3/C4/Y5/S5/S6 HYMP564S64CP6-E3/C4/Y5/S5/S6 HYMP512S64CP8-E3/C4/Y5/S5/S6 HYMP532S64CLP6-E3/C4/Y5/S5/S6 HYMP564S64CLP6-E3/C4/Y5/S5/S6 HYMP512S64CLP8-E3/C4/Y5/S5/S6 Density 256MB 512MB 1GB 256MB 512MB 1GB Organization 32Mx64 64Mx64 128Mx64 32Mx64 64Mx64 128Mx64 # of DRAMs 4 8 16 4 8 16 # of ranks 1 2 2 1 2 2 Materials Lead free- Lead free Lead free Lead free Lead free Lead free Power Consumption Normal Normal Normal Low Low Low Notes: 1. All Hynix’ DDR2 Lead-free parts are pliant to Ro HS. This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Jul. 2007 1 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed @CL3 Speed @CL4 Speed @CL5 Speed @CL6 CL-t RCD-t RP 400 533 3-3-3 C4 (DDR2-533) 533 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 5-5-5 S5 (DDR2-800) 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps t CK ADDRESS TABLE Density 256MB 512MB 1GB Organization Ranks 32M x 64 64M x 64 128M x 64 1 2 2 SDRAMs 32Mb x 16 32Mb x 16 64Mb x 8 # of DRAMs 4 8 16 # of row/bank/column Address 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) Refresh...