HY512264SLTC Overview
This family is a 4M bit dynamic RAM organized 131,072 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. In dependant read and write of upper and lower byte is controlled by 2 separate /CAS inputs.
HY512264SLTC Key Features
- SL : Low power with self refresh