HY514404A Datasheet | Hyundai

DESCRIPTION This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and package type(SOJ, TSOP-II) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Extended data out operation Ÿ Read-modify-write Capability Ÿ TTL patible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ Max. Active power dissipation Speed 50 60 70 Power 605m W 495m W 412m W Ÿ Refresh cycle Part number HY514404A Refresh 1K Normal 16ms SL-part 128ms Ÿ JEDEC standard pinout Ÿ 20/26-pin SOJ (300mil) 20/26-pin TSOP-II (300mil) Ÿ Single power supply of 5V ± 10% Ÿ Early Write or output enable controlled write Ÿ Fast access time and cycle time Speed 50 60 70 t RAC 50ns 60ns 70ns t CAC 13ns 15ns 20ns t HPC 20ns 25ns 30ns ORDERING INFORMATION Part Name HY514404AJ HY514404ALJ HY514404AT HY514404ALT - SL : Low power with self refresh Refresh 1K 1K 1K 1K Power L-part L-part Package 20/26Pin SOJ 20/26Pin SOJ 20/26Pin TSOP-II 20/26Pin TSOP-II This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Rev.10 / Jan.97 Hyundai Semiconductor FUNCTIONAL BLOCK DIAGRAM WE CAS DQ0 ~ DQ3 4 Data Input Buffer Data Output Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Address Buffer CAS Clock Generator Cloumn Predecoder (10) Refresh Controller Refresh Counter...