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TC9204M - 4-Port 10/100/1000 Smart Ethernet Switch

General Description

TC9204M is a fully integrated 4-Port 10/100/1000 smart Ethernet switch controller designed for low cost and high performance solutions.

The chip embeds necessary SSRAM for packet buffering and MAC address table.

It provides MII / GMII interface for all ports.

Key Features

  • Stand Alone Switch On A Chip 4 Ethernet 10/100/1000 ports MII/GMII interface for all ports Four Classes of Service (CoS) selectable for each port and/or checked via IP Header and 802.1Q VLAN Tag Support 4 port-based VLANs Maximum throughput (wire speed), non head-of-line blocking architecture Embedded SSRAM for packet buffer / address table, no external memory required 8K MAC address table 25 MHz crystal input only Each port is configurable to 10 full/half duplex, 100 full/half duplex and 1000 f.

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Datasheet Details

Part number TC9204M
Manufacturer IC Plus
File Size 1.51 MB
Description 4-Port 10/100/1000 Smart Ethernet Switch
Datasheet download datasheet TC9204M Datasheet

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Part Number Description
TC9205M 5-Port 10/100/1000 Smart Ethernet Switch
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC9204M Preliminary Data Sheet 4-Port 10/100/1000 Smart Ethernet Switch Features Stand Alone Switch On A Chip 4 Ethernet 10/100/1000 ports MII/GMII interface for all ports Four Classes of Service (CoS) selectable for each port and/or checked via IP Header and 802.1Q VLAN Tag Support 4 port-based VLANs Maximum throughput (wire speed), non head-of-line blocking architecture Embedded SSRAM for packet buffer / address table, no external memory required 8K MAC address table 25 MHz crystal input only Each port is configurable to 10 full/half duplex, 100 full/half duplex and 1000 full duplex mode Flow-control ability is able to set for both full and half duplex mode Broadcast throttling Port Mirroring Serial EEPROM Interface, EEPROM is optional MDIO master for PHY configuration / polling 0.