IMD256M16R30HG8GNF-125 Overview
4Gb: x4, x8, x16 DDR3 SDRAM Features Y • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) P • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) O • Posted CAS Addictive latency (AL)
IMD256M16R30HG8GNF-125 Key Features
- 128 Meg x 4 x 8 Banks (TBD)512M8
- 64 Meg x 8 x 8 Banks (IMD256M16R30HG8GNF-125/107)256M16
- 32 Meg x 16 x 8Banks
- VDD = VDDQ = +1.5V ±0.075V
- 1.5V center-terminated push/pull I/O
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals