ICS ICS844101I-312
The ICS844101I-312 is a low phase-noise frequency margining synthesizer and is a memHiPerClockS™ ber of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS844101I-312 is provided in a 16pin TSSOP. VCO (MHz) 562.5 575 587.5 600 612.5 625 637.5 650 662.5 675 687.5 Output Divider (N) 2 2 2 2 2 2 2 2 2 2 2 Output Frequency (MHz) 281.25 287.5 293.75 300 306.25 312.5 318.75 325 331.25 337.5 343.75 % Change -10.0 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10.0 FUNCTIONAL DESCRIPTION The ICS844101I-312...| Part No. | ICS844101I-312 |
|---|---|
| Datasheet | ICS844101I-312 Download |
| Manufacturer |  ICS |
| Description | CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| Buy | Stock & Price |
FEATURES
● One 312.5MHz nominal LVDS output● Selectable crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal or LVCMOS single-ended input
● Output frequency can be varied in 2% steps ± from nominal
● VCO range: 560MHz - 690MHz
● RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.52ps (typical)
● Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V
● -40°C to 85°C ambient operating temperature
● Available in both standard and lead-free RoHS-complaint packages
GENERAL DESCRIPTION
In the default mode, the device nominally generates a 312.5MHz LVDS output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. The ICS844101I-312 is provided in a 16pin TSSOP. IC S BLOCK DIAGRAM OE CLK Pullup Pulldown PIN ASSIGNMENT GND S_LOAD S_DATA Q S_CLOCK SEL nQ OE VDDA VDD 1 2 3 4 5 6 7 8 16 1...
