ICS ICS87946-01
The ICS87946-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87946-01 has one LVPECL clock input pair. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.| Part No. | ICS87946-01 |
|---|---|
| Datasheet | ICS87946-01 Download |
| Manufacturer |  ICS |
| Description | LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR |
| Buy | Stock & Price |
FEATURES
● 10 single ended LVCMOS outputs, 7Ω typical output impedance● LVPECL clock input pair
● PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL
● Maximum input frequency: 250MHz
● Output skew: 200ps (maximum)
● Part-to-part skew: 500ps (typical)
● Multiple frequency skew: 350ps (maximum)
● 3.3V input, outputs may be either 3.3V or 2.5V supply modes
● 0°C to 70°C ambient operating temperature
● Industrial temperature information available upon request ICS87946-01
GENERAL DESCRIPTION
The ICS87946-01 has one LVPECL clock input pair. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. ,&6 The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
