ICS87949-01 Datasheet PDF (CLOCK GENERATOR)

General Description

The ICS87949-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS.

The ICS87949-01 has selectable single ended clock or LVPECL clock inputs.

The single ended clock input accepts LVCMOS or LVTTL input levels.

Key Features

15 single ended LVCMOS outputs, 7Ω typical output impedance.
Selectable LVCMOS or LVPECL clock inputs.
CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL.
PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL.
Maximum input frequency: 250MHz.
Output skew: 200ps (maximum).
Part-to-part skew: 500ps (typical).
Multiple frequency skew: 350ps (maximum).
3.3V input, outputs may be either 3.

Datasheet Details

Part number	ICS87949-01
Manufacturer	ICS
File Size	152.39 KB
Description	CLOCK GENERATOR
Datasheet	ICS87949-01 Datasheet

Part number

ICS87949-01

Manufacturer

ICS

File Size

152.39 KB

Description

CLOCK GENERATOR

Datasheet

ICS87949-01 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS87949-01 LOW SKEW ÷1, ÷2 CLOCK GENERATOR GENERAL DESCRIPTION The ICS87949-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87949-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.