ICS87973I-147 Datasheet PDF (1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER)

General Description

The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS.

The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs.

The ICS87973I-147 is a highly flexible device.

Key Features

Fully integrated PLL.
14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync.
Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs.
CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL.
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
Output frequency range: 10MHz to 150MHz.
VCO range: 240MHz to 500MHz.
Output skew: 200ps (maximum).
Cycle-to-.

Datasheet Details

Part number	ICS87973I-147
Manufacturer	ICS
File Size	308.93 KB
Description	1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Datasheet	ICS87973I-147 Datasheet

Part number

ICS87973I-147

Manufacturer

ICS

File Size

308.93 KB

Description

1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Datasheet

ICS87973I-147 Datasheet

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Part Number

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1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87931I

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER FEATURES • Fully integrated PLL • 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷ 4): 55ps (maximum) • Full 3.