ICS ICS889831
The ICS889831 is a high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer and is a member HiPerClockS™ of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS889831 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_ AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components.| Part No. | ICS889831 |
|---|---|
| Datasheet | ICS889831 Download |
| Manufacturer |  ICS |
| Description | 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER |
| Buy | Stock & Price |
FEATURES
● 4 differential LVPECL/ECL outputs● IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
● 50Ω internal input termination to VT
● Maximum output frequency: > 2.1GHz
● Output skew: 30ps (maximum)
● Part-to-part skew: 185ps (maximum)
● Additive phase jitter, RMS: 0.27ps (typical)
● Propagation delay: 570ps (maximum)
● LVPECL mode operating voltage supply range: VCC = 2.5V ± 5%, 3.3V ± 5%, VEE = 0V
● ECL mode operating voltage supply range: VCC = 0V, VEE = -3.3V ± 5%, 2.5V ± 5%
● -40°C to 85°C ambient operating temperature
● Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889831 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. ICS BLOCK DIAGRAM EN D Q LE IN VT nIN 5 0Ω PIN ASSIGNMENT nQ0 VCC Q0 nQ0 Q1 nQ1 Q1 1 nQ1 2 Q2 3 nQ2 4 16 15 14 13 12 11 10 9 5 Q3 VEE Q0 IN VT VREF_AC nIN 6 nQ3 7 VCC 8 EN 5 0Ω Q2 nQ2 ICS889831 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View VREF_AC Q3 nQ3 889831AK 1 REV.
